library ieee;
use ieee.std_logic_1164.all;
use work.count_type.all;      


entity tb_src is      -- empty entity for testbench
end tb_src;

architecture test_design of tb_src is

   signal clk_wire      :     std_ulogic     := '0';
   signal reset_wire    :     std_ulogic     := '1';
   signal q_wire        :     std_ulogic_vector(max-1 downto 0); 

   component sync_reset_counter 
   port(
      clk          :     in std_ulogic;
      reset        :     in std_ulogic;
      q            :     out std_ulogic_vector
      );
   end component;

begin
   UUT : sync_reset_counter
   port map ( clk     =>  clk_wire,
              reset   =>  reset_wire,
              q       =>  q_wire
            );

   clk_wire <= not(clk_wire) after 10 ns;    -- creating clock

   process
   begin
      wait for 15 ns;
      reset_wire <= '0';
      wait for 100 ns;
      reset_wire <= '1';
      wait for 15 ns;
      reset_wire <= '0';
      wait for 60 ns;
      wait;
   end process;

end test_design;