library ieee;
use ieee.std_logic_1164.all;

entity tb_moore2 is
end tb_moore2;

architecture test_design of tb_moore2 is

   signal reset_wire : std_ulogic;   
   signal clk_wire : std_ulogic   :='0';
   signal z_wire   : std_logic;

   component moore2
   port(
      RESET  : in std_ulogic;
      CLK    : in std_ulogic;
      Z      : out std_ulogic
      );
   end component;

begin

   UUT : moore2
      port map(RESET => reset_wire,
               CLK   => clk_wire,
                 Z   => z_wire
               );

   clk_wire <= not(clk_wire) after 10 ns;   -- creating clock

   process
   begin
      reset_wire <= '1';
      wait for 5 ns;
      reset_wire <= '0';
      wait for 50 ns;
      wait;
   end process;

end test_design;