library ieee;
use ieee.std_logic_1164.all;

entity tb_moore is
end tb_moore;

architecture test_design of tb_moore is

   signal reset_wire : std_ulogic; 
   signal x_wire     : std_ulogic;  
   signal clk_wire   : std_ulogic   :='0';  -- initial value
   signal z_wire     : std_ulogic;

   component moore
   port(
      RESET  : in std_ulogic;
      X      : in std_ulogic;
      CLK    : in std_ulogic;
      Z      : out std_ulogic
      );
   end component;

begin
   -- This testbench contains 3 types of concurrent statements:
   -- 1. component instantiation
   -- 2. concurrent signal assignment statement to create clock
   -- 3. process, which is a concurrent statement, composed of
   --    sequentially-executed statements

   UUT : moore
   -- component instantiation with explicit port mapping
   -- formal parameter => actual parameter
   port map (RESET => reset_wire,
             X     => x_wire,
             CLK   => clk_wire,
             Z     => z_wire
            );

   clk_wire <= not(clk_wire) after 10 ns;   -- creating clock

   process   
   begin
       reset_wire <= '1';
       x_wire <= '0';
       wait for 5 ns;
       reset_wire <= '0';
       x_wire <= '1';
       wait for 20 ns;
       x_wire <= '0';
       wait for 20 ns;
       x_wire <= '1';
       wait for 60 ns;
       wait;           
   end process;

end test_design;