library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_psa_1 is  
end tb_psa_1;

architecture test_design of tb_psa_1 is

   signal addend_one : std_ulogic_vector(3 downto 0) := "0001";
   signal addend_two : std_ulogic_vector(3 downto 0) := "0100";
   signal sum        : std_ulogic_vector(3 downto 0);
   signal clk        : std_ulogic := '0';

   constant incr : std_ulogic_vector(3 downto 0) := "0001";
  

   component easy_adder 
     port(
       addend_one         : in std_ulogic_vector(3 downto 0);
       addend_two         : in std_ulogic_vector(3 downto 0);
       sum                : out std_ulogic_vector(3 downto 0)
       );

   end component;

begin

   UUT : easy_adder 
   port map (addend_one => addend_one, addend_two => addend_two,  
	     sum => sum);

   clk <= not(clk) after 10 ns;


   test:process
   begin
      addend_one <= "0100";
      addend_two <= "0000";
      for i in 1 to 10 loop
         wait until rising_edge(clk);    -- ok if not synthesizing
         addend_two <= std_ulogic_vector((unsigned(addend_two) + unsigned(incr))
);
      end loop;
      wait;
   end process test;

end test_design;