library ieee;
use ieee.std_logic_1164.all;

entity tb_psa is  
end tb_psa;

architecture test_design of tb_psa is

  signal addend_one : std_ulogic_vector(3 downto 0) := "0001";
  signal addend_two : std_ulogic_vector(3 downto 0) := "0100";
  signal sum        : std_ulogic_vector(3 downto 0);

  component easy_adder 
    port(
      addend_one         : in std_ulogic_vector(3 downto 0);
      addend_two         : in std_ulogic_vector(3 downto 0);
      sum                : out std_ulogic_vector(3 downto 0)
      );

  end component;

begin

   UUT : easy_adder 
   port map (addend_one => addend_one, addend_two => addend_two,  
	     sum => sum);

   process
   begin
      addend_one <= "0001";		-- addend_one = 1 
      addend_two <= "0100";		-- addend_two = 4	
      wait for 30 ns;		        -- sum = 5 ; 
      addend_one <= "1010";		-- addend_one = 10 
      addend_two <= "1010";		-- addend_two = 10 	
      wait for 10 ns;	        	-- sum = 4 since the addition is modulo-16; 
      addend_one <= "0101";		-- addend_one = 5
      wait;          		        -- sum = 15;  
   end process;

end test_design;