library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_left_rotator is
end tb_left_rotator;

architecture test_design of tb_left_rotator is

  signal n    : std_ulogic_vector(4 downto 0); 
  signal din  : std_ulogic_vector(31 downto 0);
  signal dout : std_ulogic_vector(31 downto 0);

  component left_rotator
    port (n    : in  std_ulogic_vector(4 downto 0); 
          din  : in  std_ulogic_vector(31 downto 0);
          dout : out std_ulogic_vector(31 downto 0)
         );
  end component;
  
begin
  UUT: left_rotator
  port map (n => n, din => din, dout => dout);
  
  process
  begin
    din <= "00000000000000000000000000000001";
    n <= "00010";
    wait for 10 ns;
    n <= "00100";
    wait for 10 ns;
    n <= "01000";
    wait for 10 ns;
    n <= "10000";
    wait for 10 ns;
    n <= "00001";
    wait;
  end process;

end test_design;