library ieee;
use ieee.std_logic_1164.all;

entity latch_example is
  port(  a : in std_ulogic; 
         b : in std_ulogic;
         Y : out std_ulogic;
         Z : out std_ulogic);
end;

architecture behavior of latch_example is
begin

   latch_proc: process (a,b)
   begin
     if a = '1' then
        Y <= b;
        Z <= not b;
     else 
        Z <= b;
     end if; 
   end process latch_proc;
						
end behavior;