library ieee;
use work.count_type.all;
use ieee.std_logic_1164.all;

-- up counter with synchronous reset
entity sync_reset_counter is
  port (clk, reset: in std_ulogic; 
	q: out std_ulogic_vector(max-1 downto 0)
  );
end sync_reset_counter;

architecture behavior of sync_reset_counter is
  signal current_state, next_state : std_ulogic_vector(max-1 downto 0);

begin

  -- process for incrementing the counter
  count_up: process (reset, current_state) 
  begin
    if reset = '1' then
      for i in 0 to max-1 loop
        next_state(i) <= '0'; -- sync_reset it back to all 0's
      end loop;
    else
      next_state <= incr (current_state);
    end if;
  end process count_up;

  -- feeding the counter value to output
  q <= current_state;

  -- process to represent the 5-bit flip-flop
  sync: process
  begin
    wait until rising_edge(clk);
    current_state <= next_state;
  end process sync;

end behavior;