-- 4-bit adder using the VHDL process construct

library ieee;
use ieee.std_logic_1164.all;

entity process_4_bit_adder is
  port ( addend_one  : in std_ulogic_vector(3 downto 0);
         addend_two  : in std_ulogic_vector(3 downto 0);
         carry_in    : in std_ulogic  ;
         sum         : out std_ulogic_vector(3 downto 0);
         carry_out   : out std_ulogic) ;
end process_4_bit_adder;

-- module behavior
architecture structural of process_4_bit_adder is
begin

  add_4_bit_process: process(addend_one, addend_two, carry_in)
     variable carry: std_ulogic_vector(4 downto 0);
  begin
     carry(0) := carry_in;
     for i in 0 to 3 loop
	sum(i) <= addend_one(i) xor addend_two(i) xor carry(i);
	carry(i+1) := (addend_one(i) and addend_two(i)) or 
                      (addend_one(i) and carry(i)) or 
		      (addend_two(i) and carry(i));
     end loop;
     carry_out <= carry(4);
   end process add_4_bit_process;

end structural;