-- adder using the VHDL '+' operator
-- input is two 4-bit unsigned addends
-- output is a 5-bit sum

-- include libraries
library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;  -- required for using + 

-- entity interface
entity easy_adder2 is
  port ( addend_one : in std_ulogic_vector(3 downto 0);                   
         addend_two : in std_ulogic_vector(3 downto 0);
         sum        : out std_ulogic_vector(4 downto 0)                    
       );
end easy_adder2;

-- entity behavior
architecture behavioral of easy_adder2 is
   begin
      sum <= std_ulogic_vector(('0' & unsigned(addend_one)) + ('0' & unsigned(addend_two)));       -- concurrent signal assignment; & is the concatanation operator 
end behavioral;