library ieee;
use ieee.std_logic_1164.all;

entity two is
  port (x,y : in std_logic;
          z : out std_logic);
end two;

architecture behavioral of two  is

begin

     p1: process(x)
     begin
       z <= x ;
     end process p1;

     p2: process(y)
     begin
       z <= y ;
     end process p2;

end behavioral;
