library ieee;
use ieee.std_logic_1164.all;

-- moore: value of output Z depends on value of CURRENT_STATE only.

entity MOORE5 is
  port(RESET, CLK : in std_ulogic; Z: out std_ulogic);
end MOORE5;

architecture BEHAVIOR of MOORE5 is
  type state_type is (s0, s1);
  signal CURRENT_STATE, NEXT_STATE: state_type;
begin

  -- unclocked process to assign output Z.
  combin0: process (CURRENT_STATE)
  begin
    case CURRENT_STATE is
      when s0 =>
        Z <= '0';        -- unregistered output
      when s1 =>
        Z <= '1';
    end case;
  end process combin0;

  -- unclocked process to assign NEXT_STATE.
  combin1: process (CURRENT_STATE)
  begin
    case CURRENT_STATE is
      when s0 =>
        NEXT_STATE <= s1;
      when s1 =>
        NEXT_STATE <= s0;
    end case;
  end process combin1;

  -- From clocked process sr, CURRENT_STATE is 
  -- synthesized as the state register with asynchronous reset.
  sr: process (RESET, CLK)
  begin
     if (RESET = '1') then 
        CURRENT_STATE <= s0;                               
     elsif rising_edge(CLK) then
        CURRENT_STATE <= NEXT_STATE;
     end if;
  end process sr;                          

end BEHAVIOR;