library ieee;
use ieee.std_logic_1164.all;

-- moore: value of output Z depends on value of STATE only.

entity MOORE4 is
  port(RESET,CLK : in std_ulogic; Z: out std_ulogic);
end MOORE4;

architecture BEHAVIOR of MOORE4 is
  type state_type is (s0, s1);
  signal STATE: state_type;
begin
   -- One clocked  process moore state machine 
   p0: process(RESET, CLK) 
   begin
      if RESET='1'  then              
	 STATE <= s0;                 
             Z <= '0';
      elsif rising_edge(CLK) then
	 case STATE is                
	    when s0 =>
	       Z <= '0';
	       STATE <= s1;
	    when s1 =>
	       Z <= '1';
	       STATE <= s0;
	 end case;
      end if;
   end process p0;
end BEHAVIOR ;