library ieee;
use ieee.std_logic_1164.all;

-- moore: value of output Z depends
--        on value of CURRENT_STATE

entity MOORE2 is
  port(RESET,CLK : in std_ulogic; Z: out std_ulogic);
end;

architecture BEHAVIOR of MOORE2 is
  type state_type is (s0, s1);
  signal CURRENT_STATE, NEXT_STATE: state_type;
begin

   -- unclocked process to assign NEXT_STATE.
   combin: process (CURRENT_STATE)
   begin
     case CURRENT_STATE is
       when s0 =>
	 NEXT_STATE <= s1;
       when s1 =>
	 NEXT_STATE <= s0;
     end case;
   end process combin;


   -- From clocked process sr, CURRENT_STATE is 
   -- synthesized as the state register with asynchronous reset.
   sr: process (RESET, CLK)
   begin
      if (RESET = '1') then 
	 CURRENT_STATE <= s0;                               
      elsif rising_edge(CLK) then
	 CURRENT_STATE <= NEXT_STATE;
      end if;
   end process sr;                         


   with CURRENT_STATE select     -- selected signal assignment 
      Z <= '0' when s0,          -- non-registered outputs 
	   '1' when s1;
  
end BEHAVIOR;