library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
  
entity integer_example  is
   port(a_in     : in std_ulogic_vector ; 
        b_in     : in std_ulogic_vector ; 
        a_out    : out integer ; 
        b_out    : out integer range 0 to 2147483647  
       );
end integer_example;

architecture behavior of integer_example is
begin
   a_out <= to_integer(unsigned(a_in));
   b_out <= to_integer(unsigned(b_in));
end behavior;