-- one-bit adder slice

--include library
library ieee;
use ieee.std_logic_1164.all;  

-- entity interface
entity full_adder is
   port (a_one   :in  std_ulogic;
         a_two   :in  std_ulogic;
         c_in    :in  std_ulogic;
         s       :out std_ulogic;
         c_out   :out std_ulogic);
end full_adder;

-- entity behavior
architecture structural of full_adder is
begin
   s <= a_one xor a_two xor c_in;
   c_out <= (a_one and a_two) or (a_one and c_in) or (a_two and c_in);  
end structural;