library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity functional_rtl is
  port(RESET: in  std_ulogic;
       CLK  : in  std_ulogic;
       a    : in  std_ulogic_vector(3 downto 0);
       b    : in  std_ulogic_vector(3 downto 0);
       c    : out std_ulogic_vector(3 downto 0));
end functional_rtl;

architecture BEHAVIOR of functional_rtl  is
   type state_type is (s0, s1);
   signal CURRENT_STATE: state_type;
   signal NEXT_STATE   : state_type;
   signal c_next       : std_ulogic_vector(3 downto 0);
begin

   p0: process(CURRENT_STATE,a,b)   -- unclocked process p0 for combinational elements 
   begin
      case CURRENT_STATE is                
	 when s0 =>
	    c_next <= std_ulogic_vector((unsigned(a) + unsigned(b)));
	    NEXT_STATE <= s1;
	 when s1 =>
	    c_next <= std_ulogic_vector((unsigned(a) - unsigned(b)));
	    NEXT_STATE <= s0;
      end case;
   end process p0;

   p1: process(RESET, CLK)   -- clocked process p1 for synchronous elements
   begin
      if RESET='1'  then              
         c <= "0000";
	 CURRENT_STATE <= s0;                 
      elsif rising_edge(CLK) then
         c <= c_next;
	 CURRENT_STATE <= NEXT_STATE;
      end if;
   end process p1;

end BEHAVIOR ;