-- combinational loop example 
library ieee;
use ieee.std_logic_1164.all;

entity combinational_loop is
   port (a: in std_ulogic;
         b: in std_ulogic;
         y: inout std_ulogic;
         z: inout std_ulogic);
end combinational_loop;

architecture behavioral of combinational_loop  is
begin

  p1: process(a,z)
  begin
     y <= a or z ;
  end process p1;

  p2: process(b,y)
  begin
     z <= b and y ;
  end process p2;

end behavioral;