-- clocked loop example 
-- include libraries
library ieee;
use ieee.std_logic_1164.all;

-- entity interface
entity clocked_loop is
   port (a: in std_ulogic;
         b: in std_ulogic;
       clk: in std_ulogic;
         y: inout std_ulogic;
         z: inout std_ulogic);
end clocked_loop;

-- module behavior
architecture behavioral of clocked_loop  is
begin

  p1: process
  begin
     wait until rising_edge(clk);
     y <= a or z ;
  end process p1;

  p2: process(b,y)
  begin
     z <= b and y ;
  end process p2;

end behavioral;