module three (clk, t, u, v, w, y, z, a,b,c,d,e,f);
   input clk;
   input [15:0] t, u, v, w, y, z;
   output [15:0] a, b, c, d, e, f; // all adders 
                                   // synthesized 
                                   // were 16 bit

   reg [15:0] d, e, f; // synthesized as 16 bit 
                       // register

   assign a = t + 6; // synthesis warning: signed 
                     // to unsigned assignment
   assign b = u + 16'b0000000000000110;
   assign c = v + 16'd6;

   always@ (posedge clk)
   begin
      d <= w + 6; // synthesis warning: signed to 
                  // unsigned assignment
      e <= y + 16'b0000000000000110;
      f <= z + 16'd6;
   end
endmodule