module two (clk, a, b, c, d, e, f);
   input clk;
   output [15:0] a, b, c, d, e, f;

   reg [15:0] d, e, f; // synthesized as 16 bit 
                       // registers

   assign a = 6; // synthesis warning: signed to 
                 // unsigned assignment
   assign b = 16'b0000000000000110;
   assign c = 16'd6;

   always@ (posedge clk)
   begin
      d <= 6; // synthesis warning: signed to 
              // unsigned assignment
      e <= 16'b0000000000000110;
      f <= 16'd6;
   end
endmodule