moduleone (clk, a, b, c, d, e, f);
  input clk;
  output [31:0] a, b, c, d, e, f;

  reg [31:0] d, e, f;

  assign a = 6; // synthesis warning: signed to 
                // unsigned assignment
  assign b = 32'b00000000000000000000000000000110;
  assign c = 32'd6;

  always@ (posedge clk)
  begin
     d <= 6; // synthesis warning: signed to 
             // unsigned assignment
     e <= 32'b00000000000000000000000000000110;
     f <= 32'd6;
  end
endmodule