-- Xilinx Vhdl produced by program ngd2vhdl C.22 -- Command: -w h.4.bit.adder.nga time_sim.vhd -- Options: -w -ti UUT -- Date: Mon Feb 02 21:26:59 2004 -- Input file: h.4.bit.adder.nga -- Output file: time_sim.vhd -- Tmp file: /LOCALS~1/Temp/xil_4 -- Design name: h_4_bit_adder -- Xilinx: C:/Fndtn -- # of Entities: 1 -- Device: 4025epg223-2 -- The output of ngd2vhdl is a simulation model. This file cannot be synthesized, -- or used in any other manner other than simulation. This netlist uses simulation -- primitives which may not represent the true implementation of the device, however -- the netlist is functionally correct. Do not modify this file. -- Model for TOC (Tristate-On-Configuration) Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity TOC is generic (InstancePath: STRING := "*"; WIDTH : Time := 0 ns); port(O : out std_ulogic := '0'); attribute VITAL_LEVEL0 of TOC : entity is TRUE; end TOC; architecture TOC_V of TOC is attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE; begin ONE_SHOT : process begin O <= '1'; if (WIDTH <= 0 ns) then O <= '0'; else wait for WIDTH; O <= '0'; end if; wait; end process ONE_SHOT; end TOC_V; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity H_4_BIT_ADDER is port ( CARRY_IN : in STD_LOGIC := 'X'; CARRY_OUT : out STD_LOGIC; ADDEND_ONE : in STD_LOGIC_VECTOR ( 3 downto 0 ); ADDEND_TWO : in STD_LOGIC_VECTOR ( 3 downto 0 ); SUM : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end H_4_BIT_ADDER; architecture STRUCTURE of H_4_BIT_ADDER is component TOC generic (InstancePath: STRING := "*"; WIDTH : Time := 0 ns); port (O : out STD_ULOGIC := '1'); end component; signal CARRY_IN_INT : STD_LOGIC; signal CARRY_OUT_1 : STD_LOGIC; signal CARRY_OUT_DUP0 : STD_LOGIC; signal ADDEND_ONE_0_INBLOCK_I : STD_LOGIC; signal ADDEND_ONE_1_INBLOCK_I : STD_LOGIC; signal ADDEND_ONE_2_INBLOCK_I : STD_LOGIC; signal ADDEND_ONE_3_INBLOCK_I : STD_LOGIC; signal ADDEND_TWO_0_INBLOCK_I : STD_LOGIC; signal ADDEND_TWO_1_INBLOCK_I : STD_LOGIC; signal ADDEND_TWO_2_INBLOCK_I : STD_LOGIC; signal ADDEND_TWO_3_INBLOCK_I : STD_LOGIC; signal CARRY_IN_INBLOCK_I : STD_LOGIC; signal CARRY_OUT_1_F : STD_LOGIC; signal CARRY_OUT_1_H1 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; signal CARRY_OUT_1_HLUT_AND0 : STD_LOGIC; signal CARRY_OUT_1_HLUT_AND1 : STD_LOGIC; signal CARRY_OUT_1_HLUT_AND2 : STD_LOGIC; signal SUM_DUP0_3_F : STD_LOGIC; signal SUM_DUP0_3_H1 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_OR6 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; signal SUM_DUP0_3_HLUT_AND0 : STD_LOGIC; signal SUM_DUP0_3_HLUT_AND1 : STD_LOGIC; signal SUM_DUP0_1_F : STD_LOGIC; signal SUM_DUP0_1_H1 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5 : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_OR6 : STD_LOGIC; signal SUM_DUP0_1_HLUT_AND0 : STD_LOGIC; signal SUM_DUP0_1_HLUT_AND1 : STD_LOGIC; signal CARRY_OUT_DUP0_F : STD_LOGIC; signal CARRY_OUT_DUP0_H1 : STD_LOGIC; signal CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; signal CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; signal CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; signal CARRY_OUT_DUP0_HLUT_AND0 : STD_LOGIC; signal CARRY_OUT_DUP0_HLUT_AND1 : STD_LOGIC; signal CARRY_OUT_DUP0_HLUT_AND2 : STD_LOGIC; signal CARRY_OUT_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_0_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_2_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; signal CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_2_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_2_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_0_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_2_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; signal SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; signal SUM_DUP0_3_HLUT_AND0_0_INV : STD_LOGIC; signal SUM_DUP0_3_HLUT_AND1_1_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3_2_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_1_INV : STD_LOGIC; signal SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; signal SUM_DUP0_1_HLUT_AND0_0_INV : STD_LOGIC; signal SUM_DUP0_1_HLUT_AND1_1_INV : STD_LOGIC; signal SUM_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; signal SUM_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; signal SUM_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; signal SUM_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; signal GTS : STD_LOGIC; signal ADDEND_TWO_INT : STD_LOGIC_VECTOR ( 3 downto 0 ); signal ADDEND_ONE_INT : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SUM_DUP0 : STD_LOGIC_VECTOR ( 3 downto 0 ); begin ADDEND_ONE_0_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_ONE(0), O => ADDEND_ONE_0_INBLOCK_I ); ADDEND_ONE_0_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_ONE_0_INBLOCK_I, O => ADDEND_ONE_INT(0) ); ADDEND_ONE_1_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_ONE(1), O => ADDEND_ONE_1_INBLOCK_I ); ADDEND_ONE_1_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_ONE_1_INBLOCK_I, O => ADDEND_ONE_INT(1) ); ADDEND_ONE_2_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_ONE(2), O => ADDEND_ONE_2_INBLOCK_I ); ADDEND_ONE_2_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_ONE_2_INBLOCK_I, O => ADDEND_ONE_INT(2) ); ADDEND_ONE_3_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_ONE(3), O => ADDEND_ONE_3_INBLOCK_I ); ADDEND_ONE_3_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_ONE_3_INBLOCK_I, O => ADDEND_ONE_INT(3) ); ADDEND_TWO_0_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_TWO(0), O => ADDEND_TWO_0_INBLOCK_I ); ADDEND_TWO_0_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_TWO_0_INBLOCK_I, O => ADDEND_TWO_INT(0) ); ADDEND_TWO_1_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_TWO(1), O => ADDEND_TWO_1_INBLOCK_I ); ADDEND_TWO_1_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_TWO_1_INBLOCK_I, O => ADDEND_TWO_INT(1) ); ADDEND_TWO_2_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_TWO(2), O => ADDEND_TWO_2_INBLOCK_I ); ADDEND_TWO_2_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_TWO_2_INBLOCK_I, O => ADDEND_TWO_INT(2) ); ADDEND_TWO_3_INBLOCK_INBUF : X_BUF port map ( I => ADDEND_TWO(3), O => ADDEND_TWO_3_INBLOCK_I ); ADDEND_TWO_3_INBLOCK_IBUF : X_BUF port map ( I => ADDEND_TWO_3_INBLOCK_I, O => ADDEND_TWO_INT(3) ); CARRY_IN_INBLOCK_INBUF : X_BUF port map ( I => CARRY_IN, O => CARRY_IN_INBLOCK_I ); CARRY_IN_INBLOCK_IBUF : X_BUF port map ( I => CARRY_IN_INBLOCK_I, O => CARRY_IN_INT ); CARRY_OUT_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI port map ( I => CARRY_OUT_DUP0, O => CARRY_OUT, CTL => CARRY_OUT_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); CARRY_OUT_1_H1_0 : X_BUF port map ( I => ADDEND_ONE_INT(1), O => CARRY_OUT_1_H1 ); CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND0_1 : X_AND2 port map ( I0 => CARRY_IN_INT, I1 => ADDEND_TWO_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND0 ); CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND1_2 : X_AND2 port map ( I0 => CARRY_IN_INT, I1 => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND1 ); CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND2_3 : X_AND2 port map ( I0 => ADDEND_TWO_INT(0), I1 => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND2 ); CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_OR3 : X_OR3 port map ( I0 => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND0, I1 => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND1, I2 => CARRY_OUT_1_FGBLOCK_LUTRAM_FLUT_AND2, O => CARRY_OUT_1_F ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_4 : X_AND3 port map ( I0 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_0_INV, I1 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_1_INV, I2 => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0 ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_5 : X_AND3 port map ( I0 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_0_INV, I1 => ADDEND_TWO_INT(0), I2 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_2_INV, O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1 ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_6 : X_AND3 port map ( I0 => CARRY_IN_INT, I1 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_1_INV, I2 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_2_INV, O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2 ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND3_7 : X_AND3 port map ( I0 => CARRY_IN_INT, I1 => ADDEND_TWO_INT(0), I2 => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND3 ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_OR4 : X_OR4 port map ( I0 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0, I1 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1, I2 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2, I3 => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND3, O => SUM_DUP0(0) ); CARRY_OUT_1_HLUT_AND0_8 : X_AND2 port map ( I0 => ADDEND_TWO_INT(1), I1 => CARRY_OUT_1_H1, O => CARRY_OUT_1_HLUT_AND0 ); CARRY_OUT_1_HLUT_AND1_9 : X_AND2 port map ( I0 => ADDEND_TWO_INT(1), I1 => CARRY_OUT_1_F, O => CARRY_OUT_1_HLUT_AND1 ); CARRY_OUT_1_HLUT_AND2_10 : X_AND2 port map ( I0 => CARRY_OUT_1_H1, I1 => CARRY_OUT_1_F, O => CARRY_OUT_1_HLUT_AND2 ); CARRY_OUT_1_HLUT_OR3 : X_OR3 port map ( I0 => CARRY_OUT_1_HLUT_AND0, I1 => CARRY_OUT_1_HLUT_AND1, I2 => CARRY_OUT_1_HLUT_AND2, O => CARRY_OUT_1 ); SUM_DUP0_3_H1_11 : X_BUF port map ( I => ADDEND_TWO_INT(3), O => SUM_DUP0_3_H1 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_12 : X_AND3 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_0_INV, I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_1_INV, I2 => ADDEND_ONE_INT(3), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_13 : X_AND3 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_0_INV, I1 => ADDEND_ONE_INT(3), I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_2_INV, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2_14 : X_AND3 port map ( I0 => ADDEND_TWO_INT(2), I1 => ADDEND_ONE_INT(2), I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2_2_INV, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3_15 : X_AND3 port map ( I0 => ADDEND_TWO_INT(2), I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3_1_INV, I2 => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_16 : X_AND3 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_0_INV, I1 => ADDEND_ONE_INT(3), I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_2_INV, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5_17 : X_AND3 port map ( I0 => ADDEND_ONE_INT(2), I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5_1_INV, I2 => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_OR6_18 : X_OR5 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0, I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1, I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2, I3 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3, I4 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_OR6 ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_OR7 : X_OR2 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_OR6, I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5, O => SUM_DUP0_3_F ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_19 : X_AND3 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_0_INV, I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_1_INV, I2 => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0 ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_20 : X_AND3 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_0_INV, I1 => ADDEND_ONE_INT(2), I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_2_INV, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1 ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_21 : X_AND3 port map ( I0 => ADDEND_TWO_INT(2), I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_1_INV, I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_2_INV, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2 ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND3_22 : X_AND3 port map ( I0 => ADDEND_TWO_INT(2), I1 => ADDEND_ONE_INT(2), I2 => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND3 ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_OR4 : X_OR4 port map ( I0 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0, I1 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1, I2 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2, I3 => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND3, O => SUM_DUP0(2) ); SUM_DUP0_3_HLUT_AND0_23 : X_AND2 port map ( I0 => SUM_DUP0_3_HLUT_AND0_0_INV, I1 => SUM_DUP0_3_H1, O => SUM_DUP0_3_HLUT_AND0 ); SUM_DUP0_3_HLUT_AND1_24 : X_AND2 port map ( I0 => SUM_DUP0_3_F, I1 => SUM_DUP0_3_HLUT_AND1_1_INV, O => SUM_DUP0_3_HLUT_AND1 ); SUM_DUP0_3_HLUT_OR2 : X_OR2 port map ( I0 => SUM_DUP0_3_HLUT_AND0, I1 => SUM_DUP0_3_HLUT_AND1, O => SUM_DUP0(3) ); SUM_DUP0_1_H1_25 : X_BUF port map ( I => ADDEND_TWO_INT(1), O => SUM_DUP0_1_H1 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_26 : X_AND3 port map ( I0 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_0_INV, I1 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_1_INV, I2 => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_27 : X_AND3 port map ( I0 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_0_INV, I1 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_1_INV, I2 => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2_28 : X_AND3 port map ( I0 => CARRY_IN_INT, I1 => ADDEND_TWO_INT(0), I2 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2_2_INV, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3_29 : X_AND3 port map ( I0 => CARRY_IN_INT, I1 => ADDEND_ONE_INT(0), I2 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3_2_INV, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_30 : X_AND3 port map ( I0 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_0_INV, I1 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_1_INV, I2 => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5_31 : X_AND3 port map ( I0 => ADDEND_TWO_INT(0), I1 => ADDEND_ONE_INT(0), I2 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5_2_INV, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_OR6_32 : X_OR5 port map ( I0 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0, I1 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1, I2 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2, I3 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3, I4 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_OR6 ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_OR7 : X_OR2 port map ( I0 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_OR6, I1 => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5, O => SUM_DUP0_1_F ); SUM_DUP0_1_HLUT_AND0_33 : X_AND2 port map ( I0 => SUM_DUP0_1_HLUT_AND0_0_INV, I1 => SUM_DUP0_1_H1, O => SUM_DUP0_1_HLUT_AND0 ); SUM_DUP0_1_HLUT_AND1_34 : X_AND2 port map ( I0 => SUM_DUP0_1_F, I1 => SUM_DUP0_1_HLUT_AND1_1_INV, O => SUM_DUP0_1_HLUT_AND1 ); SUM_DUP0_1_HLUT_OR2 : X_OR2 port map ( I0 => SUM_DUP0_1_HLUT_AND0, I1 => SUM_DUP0_1_HLUT_AND1, O => SUM_DUP0(1) ); CARRY_OUT_DUP0_H1_35 : X_BUF port map ( I => ADDEND_ONE_INT(3), O => CARRY_OUT_DUP0_H1 ); CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND0_36 : X_AND2 port map ( I0 => ADDEND_TWO_INT(2), I1 => ADDEND_ONE_INT(2), O => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND0 ); CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND1_37 : X_AND2 port map ( I0 => ADDEND_TWO_INT(2), I1 => CARRY_OUT_1, O => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND1 ); CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND2_38 : X_AND2 port map ( I0 => ADDEND_ONE_INT(2), I1 => CARRY_OUT_1, O => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND2 ); CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_OR3 : X_OR3 port map ( I0 => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND0, I1 => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND1, I2 => CARRY_OUT_DUP0_FGBLOCK_LUTRAM_FLUT_AND2, O => CARRY_OUT_DUP0_F ); CARRY_OUT_DUP0_HLUT_AND0_39 : X_AND2 port map ( I0 => ADDEND_TWO_INT(3), I1 => CARRY_OUT_DUP0_H1, O => CARRY_OUT_DUP0_HLUT_AND0 ); CARRY_OUT_DUP0_HLUT_AND1_40 : X_AND2 port map ( I0 => ADDEND_TWO_INT(3), I1 => CARRY_OUT_DUP0_F, O => CARRY_OUT_DUP0_HLUT_AND1 ); CARRY_OUT_DUP0_HLUT_AND2_41 : X_AND2 port map ( I0 => CARRY_OUT_DUP0_H1, I1 => CARRY_OUT_DUP0_F, O => CARRY_OUT_DUP0_HLUT_AND2 ); CARRY_OUT_DUP0_HLUT_OR3 : X_OR3 port map ( I0 => CARRY_OUT_DUP0_HLUT_AND0, I1 => CARRY_OUT_DUP0_HLUT_AND1, I2 => CARRY_OUT_DUP0_HLUT_AND2, O => CARRY_OUT_DUP0 ); SUM_0_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI port map ( I => SUM_DUP0(0), O => SUM(0), CTL => SUM_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_1_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI port map ( I => SUM_DUP0(1), O => SUM(1), CTL => SUM_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_2_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI port map ( I => SUM_DUP0(2), O => SUM(2), CTL => SUM_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_3_OUTBLOCK_OUT_BUF_GTS_TRI : X_TRI port map ( I => SUM_DUP0(3), O => SUM(3), CTL => SUM_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); CARRY_OUT_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_42 : X_INV port map ( I => GTS, O => CARRY_OUT_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_0_INV_43 : X_INV port map ( I => CARRY_IN_INT, O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_0_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_1_INV_44 : X_INV port map ( I => ADDEND_TWO_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND0_1_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_0_INV_45 : X_INV port map ( I => CARRY_IN_INT, O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_0_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_2_INV_46 : X_INV port map ( I => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND1_2_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_1_INV_47 : X_INV port map ( I => ADDEND_TWO_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_1_INV ); CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_2_INV_48 : X_INV port map ( I => ADDEND_ONE_INT(0), O => CARRY_OUT_1_FGBLOCK_LUTRAM_GLUT_AND2_2_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_0_INV_49 : X_INV port map ( I => ADDEND_TWO_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_0_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_1_INV_50 : X_INV port map ( I => ADDEND_ONE_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND0_1_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_0_INV_51 : X_INV port map ( I => ADDEND_TWO_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_0_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_2_INV_52 : X_INV port map ( I => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND1_2_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2_2_INV_53 : X_INV port map ( I => ADDEND_ONE_INT(3), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND2_2_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3_1_INV_54 : X_INV port map ( I => ADDEND_ONE_INT(3), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND3_1_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_0_INV_55 : X_INV port map ( I => ADDEND_ONE_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_0_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_2_INV_56 : X_INV port map ( I => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND4_2_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5_1_INV_57 : X_INV port map ( I => ADDEND_ONE_INT(3), O => SUM_DUP0_3_FGBLOCK_LUTRAM_FLUT_AND5_1_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_0_INV_58 : X_INV port map ( I => ADDEND_TWO_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_0_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_1_INV_59 : X_INV port map ( I => ADDEND_ONE_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND0_1_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_0_INV_60 : X_INV port map ( I => ADDEND_TWO_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_0_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_2_INV_61 : X_INV port map ( I => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND1_2_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_1_INV_62 : X_INV port map ( I => ADDEND_ONE_INT(2), O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_1_INV ); SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_2_INV_63 : X_INV port map ( I => CARRY_OUT_1, O => SUM_DUP0_3_FGBLOCK_LUTRAM_GLUT_AND2_2_INV ); SUM_DUP0_3_HLUT_AND0_0_INV_64 : X_INV port map ( I => SUM_DUP0_3_F, O => SUM_DUP0_3_HLUT_AND0_0_INV ); SUM_DUP0_3_HLUT_AND1_1_INV_65 : X_INV port map ( I => SUM_DUP0_3_H1, O => SUM_DUP0_3_HLUT_AND1_1_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_0_INV_66 : X_INV port map ( I => CARRY_IN_INT, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_0_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_1_INV_67 : X_INV port map ( I => ADDEND_TWO_INT(0), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND0_1_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_0_INV_68 : X_INV port map ( I => CARRY_IN_INT, O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_0_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_1_INV_69 : X_INV port map ( I => ADDEND_ONE_INT(0), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND1_1_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2_2_INV_70 : X_INV port map ( I => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND2_2_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3_2_INV_71 : X_INV port map ( I => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND3_2_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_0_INV_72 : X_INV port map ( I => ADDEND_TWO_INT(0), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_0_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_1_INV_73 : X_INV port map ( I => ADDEND_ONE_INT(0), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND4_1_INV ); SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5_2_INV_74 : X_INV port map ( I => ADDEND_ONE_INT(1), O => SUM_DUP0_1_FGBLOCK_LUTRAM_FLUT_AND5_2_INV ); SUM_DUP0_1_HLUT_AND0_0_INV_75 : X_INV port map ( I => SUM_DUP0_1_F, O => SUM_DUP0_1_HLUT_AND0_0_INV ); SUM_DUP0_1_HLUT_AND1_1_INV_76 : X_INV port map ( I => SUM_DUP0_1_H1, O => SUM_DUP0_1_HLUT_AND1_1_INV ); SUM_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_77 : X_INV port map ( I => GTS, O => SUM_0_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_78 : X_INV port map ( I => GTS, O => SUM_1_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_79 : X_INV port map ( I => GTS, O => SUM_2_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); SUM_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV_80 : X_INV port map ( I => GTS, O => SUM_3_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV ); TOC_NGD2VHDL : TOC port map (O => GTS); end STRUCTURE;