library ieee; use ieee.std_logic_1164.all; entity tb_p is end tb_p; architecture test of tb_p is signal x : std_logic; signal y : std_logic; signal z : std_logic; component two port( x : in std_logic; y : in std_logic; z : out std_logic ); end component; begin uut : two port map (x => x, y => y, z => z); m0 : process begin x <= '0'; y <= '1'; wait; end process m0; end test;