library ieee; use ieee.std_logic_1164.all; entity tb_h4ba is end tb_h4ba; architecture test_design of tb_h4ba is signal addend_one : std_ulogic_vector(3 downto 0); signal addend_two : std_ulogic_vector(3 downto 0); signal carry_in : std_ulogic; signal sum : std_ulogic_vector(3 downto 0); signal carry_out : std_ulogic; component h_4_bit_adder port( addend_one : in std_ulogic_vector(3 downto 0); addend_two : in std_ulogic_vector(3 downto 0); carry_in : in std_ulogic; sum : out std_ulogic_vector(3 downto 0); carry_out : out std_ulogic ); end component; begin UUT : h_4_bit_adder port map (addend_one => addend_one, addend_two => addend_two, carry_in => carry_in, sum => sum, carry_out => carry_out); process begin carry_in <= '0'; -- carry_in = 0 addend_one <= "1010"; -- addend_one = 10 addend_two <= "0011"; -- addend_two = 3 wait for 30 ns; -- sum = 13; carry_out = 0; carry_in <= '1'; -- carry_in = 1 wait for 30 ns; -- sum = 14; carry_out = 0; addend_one <= "0010"; -- addend_one = 2 addend_two<= "1111"; -- addend_two = 15 wait; -- sum = 2; carry_out = 1; end process; end test_design;