library ieee; use ieee.std_logic_1164.all; entity regfile is -- register file of four 32-bit registers port(reset : in std_ulogic; clk : in std_ulogic; nr_w : in std_ulogic; -- 0 to read, 1 to write enable : in std_ulogic; -- 1 to read or write addr : in std_ulogic_vector(1 downto 0); -- 2-bit address datain : in std_ulogic_vector(31 downto 0); -- data in dataout : out std_ulogic_vector(31 downto 0) -- data out ); end regfile; architecture behavior of regfile is component reg32 port(reset: in std_ulogic; clk: in std_ulogic; D: in std_ulogic_vector(31 downto 0); Q: out std_ulogic_vector(31 downto 0) ); end component; signal d0, d1, d2, d3, q0, q1, q2, q3: std_ulogic_vector (31 downto 0); begin r0: reg32 port map (reset => reset, clk => clk, D => d0, Q => q0); r1: reg32 port map (reset => reset, clk => clk, D => d1, Q => q1); r2: reg32 port map (reset => reset, clk => clk, D => d2, Q => q2); r3: reg32 port map (reset => reset, clk => clk, D => d3, Q => q3); control: process (nr_w, enable, addr, datain, q0, q1, q2, q3) -- definition of the mux/decoder begin if (enable = '1') then -- read or write if (nr_w = '0') then -- read case addr is when "00" => dataout <= q0; when "01" => dataout <= q1; when "10" => dataout <= q2; when "11" => dataout <= q3; when others => dataout <= q3; end case; d0 <= q0; -- registers keep their old value d1 <= q1; d2 <= q2; d3 <= q3; else -- write case addr is when "00" => d0 <= datain; d1 <= q1; d2 <= q2; d3 <= q3; when "01" => d0 <= q0; d1 <= datain; d2 <= q2; d3 <= q3; when "10" => d0 <= q0; d1 <= q1; d2 <= datain; d3 <= q3; when "11" => d0 <= q0; d1 <= q1; d2 <= q2; d3 <= datain; when others => d0 <= q0; d1 <= q1; d2 <= q3; d3 <= datain; end case; case addr is when "00" => dataout <= q0; -- let dataout be based on addr when "01" => dataout <= q1; -- should really just be don't care when "10" => dataout <= q2; when "11" => dataout <= q3; when others => dataout <= q3; end case; end if; else -- enable is '0': no read or write d0 <= q0; d1 <= q1; -- registers keep their old value d2 <= q2; d3 <= q3; case addr is when "00" => dataout <= q0; when "01" => dataout <= q1; -- let dataout be based on addr when "10" => dataout <= q2; -- should really just be don't care when "11" => dataout <= q3; when others => dataout <= q3; end case; end if; end process; end behavior;