library ieee; use ieee.std_logic_1164.all; entity reg32 is -- single 32-bit register port(reset: in std_ulogic; clk: in std_ulogic; D: in std_ulogic_vector(31 downto 0); Q: out std_ulogic_vector(31 downto 0) ); end reg32 ; architecture behavior of reg32 is begin synch: process (reset, clk) begin if (reset = '1') then Q <= (others => '0'); elsif rising_edge(clk) then Q <= D; end if; end process synch; end behavior;