-- adder using the VHDL '+' operator -- input is two 4-bit unsigned addends -- output is a 4-bit sum -- include libraries library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- required when using + -- entity interface entity easy_adder is port ( addend_one : in std_ulogic_vector(3 downto 0); addend_two : in std_ulogic_vector(3 downto 0); sum : out std_ulogic_vector(3 downto 0) ); end easy_adder; -- entity behavior architecture structural of easy_adder is begin sum <= std_ulogic_vector((unsigned(addend_one) + unsigned(addend_two))); end structural;