-- include libraries library ieee; use ieee.std_logic_1164.all; -- mealy: Output value Z depend on both the value of -- CURRENT_STATE and the value of the input X. -- entity interface entity MEALY is port(RESET, X, CLK: in std_ulogic; Z: out std_ulogic); end; -- entity behavior architecture BEHAVIOR of MEALY is type state_type is (s0, s1, s2, s3); signal CURRENT_STATE, NEXT_STATE: state_type; begin -- Process to hold combinational logic combin: process (CURRENT_STATE, X) begin case CURRENT_STATE is when s0 => if X = '0' then Z <= '0'; NEXT_STATE <= s0; else Z <= '1'; NEXT_STATE <= s2; end if; when s1 => if X = '0' then Z <= '0'; NEXT_STATE <= s0; else Z <= '0'; NEXT_STATE <= s2; end if; when s2 => if X = '0' then Z <= '1'; NEXT_STATE <= s2; else Z <= '0'; NEXT_STATE <= s3; end if; when s3 => if X = '0' then Z <= '0'; NEXT_STATE <= s3; else Z <= '1'; NEXT_STATE <= s1; end if; end case; end process combin; -- From clocked process sr, CURRENT_STATE is -- synthesized as the state register with asynchronous reset. sr: process (RESET, CLK) begin if (RESET = '1') then CURRENT_STATE <= s0; elsif rising_edge(CLK) then CURRENT_STATE <= NEXT_STATE; end if; end process sr; end BEHAVIOR;