-- 4-bit adder using hierarchical logic -- A 1-bit full adder is instantiated four times. -- The four 1-bit adders are wired together to comprise a 4-bit adder. -- include libraries library ieee; use ieee.std_logic_1164.all; -- interface of 4-bit adder entity h_4_bit_adder is port ( addend_one : in std_ulogic_vector(3 downto 0); -- 4-bit signal addend_two : in std_ulogic_vector(3 downto 0); -- 4-bit signal carry_in : in std_ulogic; -- 1-bit signal sum : out std_ulogic_vector(3 downto 0); -- 4-bit signal carry_out : out std_ulogic) ; -- 1-bit signal end h_4_bit_adder; -- module behavior architecture structural of h_4_bit_adder is -- Declare full_adder as a component that will be instantiated in this entity. component full_adder port (a_one: in std_ulogic; a_two: in std_ulogic; c_in : in std_ulogic; s : out std_ulogic; c_out: out std_ulogic); end component; -- Declare signals to be used as wires to connect the four instantiations of the -- full adder together to obtain the four-bit adder. The carry-out of each of -- the three lowest bit adders are each connected to the carry-in of next highest -- bit adder. signal carry_out_0: std_ulogic; -- 1-bit wire signal carry_out_1: std_ulogic; -- 1-bit wire signal carry_out_2: std_ulogic; -- 1-bit wire begin -- 4 instantiations of the full-adder component with explicit port mapping -- Formal_parameter => Actual parameter -- Formal parameter is a signal from the port of the full adder component. -- Actual parameter is a signal from either the port of the h_4_bit_adder -- or from the set of three signals declared above in the signal declaration -- section. -- Each instantiation of the full_adder component is given a unique name, i.e., fa0. fa0: full_adder port map (a_one => addend_one(0), a_two => addend_two(0), c_in => carry_in, s => sum(0), c_out => carry_out_0); fa1: full_adder port map (a_one => addend_one(1), a_two => addend_two(1), c_in => carry_out_0, s => sum(1), c_out => carry_out_1); fa2: full_adder port map (a_one => addend_one(2), a_two => addend_two(2), c_in => carry_out_1, s => sum(2), c_out => carry_out_2); fa3: full_adder port map (a_one => addend_one(3), a_two => addend_two(3), c_in => carry_out_2, s => sum(3), c_out => carry_out); end structural;