library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity functional_rtl is port(RESET: in std_ulogic; CLK : in std_ulogic; a : in std_ulogic_vector(3 downto 0); b : in std_ulogic_vector(3 downto 0); c : out std_ulogic_vector(3 downto 0)); end functional_rtl; architecture BEHAVIOR of functional_rtl is type state_type is (s0, s1); signal STATE: state_type; begin p0: process(RESET, CLK) begin if RESET='1' then STATE <= s0; c <= "0000"; elsif rising_edge(CLK) then case STATE is when s0 => c <= std_ulogic_vector((unsigned(a) + unsigned(b))); STATE <= s1; when s1 => c <= std_ulogic_vector((unsigned(a) - unsigned(b))); STATE <= s0; end case; end if; end process p0; end BEHAVIOR ;