Can you give a combinational loop example?

This source code will produce a combinational loop. 





The delay report will denote a loop. 

To eliminate the combinational loop, we can add the needed rising-edge-triggered register by using a
wait until rising_edge(clk)  statement in the source code.  We obtain a clocked process in which
signals assigned to are synthesized as registers.  The signal y is now synthesized as a register instead          
of as a wire in the unclocked process in the first example.





The delay report now doesn't indicate a loop.