• How can I display signals from an module instantiated in my design on the wave diagram when running ModelSim?
• How can I set a breakpoint when running ModelSim?
• How can I obtain code coverage information in ModelSim?

In ModelSim,

• To view the signals window, from the ModelSim Main window menu, choose View > Signals.
  
  
• To view the wave window, from the ModelSim Main window menu, choose View > Wave.
  
  
• From the signals window menu, choose Add > Wave > Signals in Region.
  
  
• To run the simulation to the end, enter
  run  -all
  at the ModelSim prompt in the ModelSim Main window.
  
  
• To restart the run, from the ModelSim Main window menu, choose Run > Restart..., and when the Restart window appears, select the Restart button.
  
  
• To delete the signals presently listed in the wave window, from the wave menu choose Edit > Select All.  Then from the wave menu choose Edit > Cut.
  
  
• To view the structure window, from the ModelSim Main window menu, choose View > Structure.
  
  
• In the structure window, select uut:h4ba.  The signals in the h4ba environment will be displayed in the signals window.
  
  
• From the signals window menu, choose View > Wave > Signals in Region.
  
  
• To run the simulation for 200 ns, enter 
  run  200 
  at the ModelSim prompt in the ModelSim Main window.
  
  
• To quit ModelSim, from the ModelSim Main window menu, choose File > Quit

You may want to occasionally print out the simulation results that appear in the wave window.  You can use the zoom feature from the wave menu to obtain the proper zoom.  To print the wave, from the wave menu, select File > Print Postscript...  When the Write Postscript window opens, select File name: and type in a name for the file name, i.e., wave1.ps, and select ok.  Only the portion of the wave that is presently viewable will be printed out.  If the waveform is long, you will have to use more than one page.  To set the laser printer destination, in a xterm window, use the command, setenv PRINTER printername, where printername is the name of the printer that you want to print to .  To view and print out a postscript file, you can use ghostview by typing the command, ghostview wave1.ps in a xterm window, where wave1.ps is the name of your postscript file.  To print out the postscript file in ghostview, choose File > Print..., type the printer name in the popup window and select ok.

Note: Simulation can also be performed on the output of the synthesis tool.  This is called gate-level simulation as opposed to RTL simulation performed in this tutorial.  Gate-level simulation is more accurate, but takes longer than RTL simulation.   Gate-level simulation will not be performed in this tutorial.

4.   Synthesis: Synopsys Design Compiler

1. Be sure you have copied full.adder.vl and h4ba.vl
   
   
2. Copy the synthesis script file, h4ba.script to the directory that you are working in.  Read the contents of the synthesis script file, which contains commands and accompanying commented information.  Synopsys Design Compiler can be run in two different modes: dcsh and Tcl (Tool Command Language).  We will use Tcl mode.  Tcl is a language widely used in EDA (electronic design automation) tools including ModelSim.
   
   
3. At the unix shell prompt, type,
   unlimit
   
   
4. At the unix shell prompt, type,
   prep  synopsys
   
   
5. At the unix shell prompt, type,
   nice   dc_shell-t
   
   
6. To run the synthesis script, at the dc_shell-t prompt, type,
   source  h4ba.script
   Some files, as commented in the script file, will be generated, including area and timing reports for the hierarchical four-bit adder, which are contained in the files, h4ba.area.rpt and h4ba.timing.rpt.

5.   Four-bit Adder using an always block

The Verilog description of a 4-bit adder using a process with a sensitivity list is p4ba.vl.  The sensitivity list is to the right of always@.  For an unclocked always block (no clock in the sensitivity list), primary input signals to the unclocked always block should be placed in the sensitivity list.  Primary input signals are signals that are read in the always block that are generated outside of the always block.  Since the signals, addend_one, addend_two, and carry_in are primary inputs to this unclocked always block, they are included in the sensitivity list.  Whenever one of the signals in the sensitivity list changes value, the always block will be executed.  The assignment statements in the unclocked process use the blocking assignment operator, =.  Signals written to with the blocking assignment operator are updated instantaneously.  Combinational logic (unclocked always block (no clock in the sensitivity list)) should be described using the blocking assignment operator.  In an unclocked always block, statements are executed sequentially. The other type of Verilog assignment operator is the non-blocking assignment operator, <=.  When a signal is written to with the non-blocking assignment operator, it is scheduled to be assigned the new value at the end of the current time unit.  Sequential logic (clocked always block (clock in the sensitivity list)) should be described using the nonblocking assignment operator.  In a clocked process using only the nonblocking assignment operator, all assignments are executed concurrently and the order does not matter.  In a clocked process, only the clock and reset (if the reset is asynchronous) should be included in the sensitivity list.

In the Verilog module, sum, carry_out, and carry are declared to be of type reg because they are assigned to in the always block.  No registers will be synthesized as no edge is specified in the event specification list (sensitivity list). 

An integer type is used as the for loop index.  The integer type is a 32-bit signed number.  Use of the integer type should be reserved for testbenches and for use as a for loop index. 

The for loop construct should only be used for iteration over space such as to assign to the bits as in this example code.  The for loop construct should not be used to try to iterate over time.  It's possible for the synthesis tool to not flag use of a for loop to iterate over time as an error; the synthesis tool may just hang in the compile operation.  Hence, it's up to the designer to avoid this pitfall.  Use of a loop state as one of your states in a state machine that increments a counter each clock cycle is a preferable method to iterate over time.  An if statement can be used in the state to synthesize a comparator to check if the count equals the loop upper limit.  Try to always think what hardware will result in synthesis from your code.

6.   A few additional adder examples

• adder_variation1.vl:  Two parallel 32-bit adders, each using the + operator.
• adder_variation2.vl:  One 32-bit addition using a for loop.
• adder_variation3.vl:  One 32-bit adder using a function; the function call precedes the function code.
• adder_variation4.vl:  One 32-bit adder using a function; the function code precedes the function call.

7.   State Machines

• Moore state machine:  moore.vl .  The value of output Z depends on the value of CURRENT_STATE.  The fsm is composed of two always blocks.  One unclocked always block is used to hold the combinational elements and one clocked always block is used to hold the synchronous elements.  The always block to hold the combinational elements uses a sensitivity list which is comprised of signals read in the always block, X and CURRENT_STATE.  Signals assigned to in an unclocked always block are synthesized as wires if no memory is inferred or as latches if memory is inferred.  In this unclocked always block, Z and NEXT_STATE are synthesized as wires.  The clocked always block to hold the sequential elements uses the keyword posedge to signify the rising edge and using it in the second always block enables synthesis of CURRENT_STATE as the state register.  When the value of the signal CLK changes from 0 to 1, CURRENT_STATE is scheduled to be assigned the value of NEXT_STATE.  Signals assigned to in a clocked always block enables synthesis as registers.  CURRENT_STATE is synthesized as the state register of the state machine.  This state machine uses state machine design style 1 from the list below.
  Some possible state machine design styles:
  1. One unclocked always block and one clocked always block.
     • One unclocked always block to assign output and to assign next state.
     • One clocked always block to update state register.
     • moore1.vl
     • tb_moore1.vl
     • moore1.script
  2. Two always blocks and a signal assignment statement.
  • One unclocked always block to assign next state.
  • One clocked always block to update state register.
  • One signal assignment statement to assign output.
  • moore2.vl
  • tb_moore2.vl
  • moore2.script
  3. Two clocked always blocks and one unclocked always block.
     • One clocked always block to update state register.
     • One unclocked always block to assign next state.
     • One clocked always block to register output.
     • moore3.vl
     • tb_moore3.vl
     • moore3.script
  4. One clocked always block.
  • moore4.vl
  • tb_moore4.vl
  • moore4.script
  5. Two unclocked always blocks and one clocked always block.
  • One unclocked always block to assign output.
  • One unclocked always block to assign next state.
  • One clocked always block to update state register.
  • moore5.vl
  • tb_moore5.vl
  • moore5.script
  
  
• Mealy state machine:  mealy.vl.  The output value Z depends on both the value of CURRENT_STATE and the value of the input X.

A sample testbench for the moore module is, tb_moore.vl.
Suppose that you want to view on the wave timing diagram the six signals from the moore state machine: RESET_N, X, CLK, Z, NEXT_STATE, and CURRENT_STATE.
One method to do this is to use a .do macro file.  Another method is to use the window menus.

• To use a .do macro file for the moore state machine, the steps are:
  
  
  1. Copy the .do file, moore.do, to the directory that you are running ModelSim.
     
     
  2. Load the tb_moore module into Modelsim using the vsim tb_moore command.
     
     
  3. In the ModelSim main window, type the command,
     do moore.do
  
  
• To use the window menus for the moore state machine, the steps are:
  
  
  1. From the ModelSim Main window menu, choose View Structure.
     
     
  2. From the ModelSim Main window menu, choose View Signals.
     
     
  3. From the ModelSim Main window menu, choose View Wave.
     
     
  4. In the Structure window, select uut: moore.
     
     
  5. The five signals of interest will be displayed in the Signals window.
     
     
  6. From the Signals window menu, choose Add > Wave > Signals In Region.
     
     
  7. The five signals of interest will be displayed in the wave timing diagram.

A Synopsys Design Compiler synthesis script file for the moore state machine is moore.script.

8.   Counter using a function

• An example of the use of a function in Verilog is the counter source code, sync_reset_counter.vl. 

  The syntax for defining a function is:
  
  function [ range_or_type ] function_identifier ;
      function_item_declaration
      statement
  endfunction
  
  

  • The declaration begins with the keyword function.  The range is where the number of bits contained in the output value is declared. 
  • The range is followed by the name of the function and a semicolon. 
  • The function_item_declaration is where the inputs are declared in the order in which they are used in the function.
  • The return value is assigned to the function name in the statement section of the function.


• A sample Verilog testbench for the counter is  tb_src.vl. 

9.   Register file example

10.   Functional RTL

• One always block.
  • Using the state machine design style 4 in moore4.vl and defining the datapath operations in each state, as in the frtl1 module in, frtl1.vl, is a popular style of design, functional RTL style. 
  • testbench: tb.frtl1.vl.
  • synthesis script: frtl1.script.
• Two always blocks.
  • Some designers prefer to keep sequential elements in a separate always block from the combinational elements.  An example is the module in frtl2.vl.  The default case in the combinational always block is needed to avoid latches being synthesized for the signals assigned to in the always block.   This style is more difficult than the frtl1 style in trying to avoid combinational loops and unwanted latches.
  • testbench: tb.frtl2.vl.
  • synthesis script: frtl2.script.
• Three always blocks.
  • One clocked always block for state register.
  • One unclocked always block for fsm combinational logic.
  • One clocked always block for non-fsm registers and combinational logic.
  • module: frtl3.vl.
  • testbench: tb.frtl3.vl.
  • synthesis script: frtl3.script.
• Four always blocks.
  • One clocked always block for state register.
  • One unclocked always block for fsm combinational logic.
  • One clocked always block for non-fsm registers.
  • One unclocked always block for non-fsm combinational logic.
  • module: frtl4.vl.
  • testbench: tb.frtl4.vl.
  • synthesis script: frtl4.script.

11.   Notes

• Unix process note.
• Cpu limit note.
• Latch note.
• Combinational loop note.
• Integer note.