Verilog   bitwise   and   logical   negation   operators

There are two negation operators:

  • logical negation !
    Inverts only least significant bit.
    i.e.,   a  =  00;   b =  ! a =  01;

  • bitwise negation ~
    Inverts all bits.
    i.e.,   a  =  00;   c  =  ~ a  =  11;

  • 2.bit.negation.vl
  • tb.2.bit.negation.vl