module moore4 (RESET_N, CLK, X, Z); input RESET_N, CLK, X; output Z; reg Z; // Z and STATE are assigned in always block => type reg. reg [1:0] STATE; parameter s0=2'b00, // 1'b0 denotes one bit with the value 0 in binary notation. s1=2'b01, s2=2'b10, s3=2'b11; always @ (posedge CLK or negedge RESET_N) if (~ RESET_N) // Asynchronous active low reset. begin Z <= 1'b0; STATE <= s0; end else case (STATE) s0: begin Z <= 1'b0; // Registered output Z. STATE<=(X==1'b0) ? s0 : s2; // State register STATE end s1: begin Z <= 1'b1; STATE=(X==1'b0) ? s0 : s2; end s2: begin Z <= 1'b1; STATE=(X==1'b0) ? s2 : s3; end s3: begin Z <= 1'b0; STATE=(X==1'b0) ? s3 : s1; end endcase endmodule