# moore.script : dc_shell-t script for moore state machine. # two procedures: # 1. set_variables procedure: sets some variables. # 2. synthesize procedure: synthesizes moore # state machine. # one verilog source code file used: # 1. moore.vl : moore state machine. proc set_variables {} { # Declare some global variables. global search_path global link_library global target_library global synthetic_library global symbol_library global compile_new_optimization global synlib_prefer_ultra_license global hdlin_report_inferred_modules global fsm_auto_inferring global hdlin_report_fsm global hdlin_infer_enumerated_types # Set some variables. set search_path {.} #should also include libraries/syn path # class.db is a standard cell library in Synopsys database format that # the design will be mapped to in the compile command of the script. set target_library class.db set link_library class.db set symbol_library class.sdb # Set the DC Ultra optimization mode and checkout the DC Ultra license. set_ultra_optimization true # Set which optimization algorithms Design Compiler uses. When true, # the new optimization algorithms in Design Compiler are turned on. # The new optimization algorithms leverage a gain-based delay # model that is automatically derived using library analysis. set compile_new_optimization true # Check out a DesignWare Foundation license. set synlib_prefer_ultra_license true # DesignWare Foundation is set as the synthetic library. set synthetic_library dw_foundation.sldb set link_library [ concat $link_library $synthetic_library ] set fsm_auto_inferring true set hdlin_report_fsm true set hdlin_infer_enumerated_types true } proc synthesize {} { # Generate a listing of licenses in use. redirect moore.license.rpt { list_license } # The file, moore.vl, is checked for errors using the analyze command. # If there's no errors, the verilog is translated to an intermediate format. # The messages generated by the analyze command are redirected to a file, # moore.analyze.rpt. echo "analyze command with moore.vl started." redirect moore.analyze.rpt { set moore_analyze_variable [ analyze -f verilog moore.vl ] } if {$moore_analyze_variable == 1} then { echo "analyze command with moore.vl successfully executed." } else { echo "The analyze command with moore.vl generated at least one error." set strings [exec grep Error moore.analyze.rpt] echo "Error message(s) from analyze moore.vl command:" puts $strings echo "Returning from synthesize procedure due to analyze moore.vl error(s)." return } echo "elaborate command with the moore module started." redirect moore.elaborate.rpt { set moore_elaborate_variable [ elaborate moore ] } if {$moore_elaborate_variable == 1} then { echo "elaborate command with moore successfully executed." } else { echo "The elaborate command with moore module generated at least one error." set strings [exec grep Error moore.elaborate.rpt] echo "Error message(s) from elaborate command with moore module:" puts $strings echo "Returning from synthesize procedure due to elaborate moore error(s)." return } current_design moore set_local_link_library class.db # Obtain a report to see if there are any combinational loops. # If there is a combinational loop the report will state # that a timing loop is detected. # If there is no combinational loop the report will state # that no loops were detected. redirect moore.loops.rpt { report_timing -loops } # Check for unwanted latches. The file, moore.latch.rpt, should be an # empty file, signifying no latches. redirect moore.latch.rpt { all_registers -level_sensitive } create_clock CLK -period 4 # Minimize area for a given timing constraint. set_max_area 0.0 # The design is mapped and optimized to the class # standard cell library using the compile command. # The compile log messages are redirected to the file, moore.compile.rpt. # Other possible choices of map_effort besides high are medium and low. echo "compile command with the moore module started." redirect moore.compile.rpt { set moore_compile_variable [ compile -map_effort low ] } if {$moore_compile_variable == 1} then { echo "compile command with moore successfully executed." } else { echo "The compile command with moore module generated at least one error." set strings [exec grep Error moore.compile.rpt] echo "Error message(s) from compile command with moore module:" puts $strings echo "Returning from synthesize procedure due to compile moore error(s)." return } # The area report is written to file. # Obtain the area in units of gates (two-input nand gates). # The area is specified in the report as the total cell area. redirect moore.area.rpt { report_area } # The timing report is written to file. # Reports the longest true path delay in the design in nanoseconds. # In the report, if the slack is negative, the design's timing as # specified in the set_max_delay command for a combinational design # or in a create_clock command for a synchronous design is not reached. redirect moore.timing.rpt { report_timing -true } # Generate schematic file, moore.ps, with critical path highlighted. create_schematic highlight_path -critical_path plot -output moore.ps # Generate a cross-reference report between schematic # objects and sheets on which they occur. redirect moore.xref.rpt { report_xref } # Check design for warnings and write output to file moore_warnings. # An empty file signifies no warnings. redirect moore.warnings.rpt { check_design } # Obtain a report summarizing information on how well # the design meets constraints that were specified. redirect moore.constraints.rpt { report_constraints } # Obtain a report displaying some information on the current design. redirect moore.design.rpt { report_design } # Obtain a report displaying attributes of the current design. redirect moore.attributes.rpt { report_attributes } # Write a report listing the number of each type of cell used in the design. redirect moore.reference.rpt { report_reference } # Write a report listing the number and type of designware components # implemented in the design for the arithmetic operators, +, -, *, <, >, etc. # In addition this report would include any resource-sharing information. # The report would also include other designware components implemented such # as muxes. Since this design does not include any arithmetic operator, # the report will be empty. redirect moore.resources.rpt { report_resources -hierarchy } # Obtain a state machine report. redirect moore.fsm.rpt { report_fsm } # Write the design to the file moore.db in Synopsys internal database format. # The -hierarchy option is only needed when modules are instantiated. # To read the design back into dc_shell-t, the command is, read_db moore.db. write -hierarchy -output moore.db echo "script completed." } set_variables synthesize exit