module frtl4 (RESET_N,CLK,a,b,c,count);
input RESET_N, CLK;
input [5:0] a, b;
output [5:0] c;
output [1:0] count;
reg [5:0] c, next_c;
reg [1:0] count, next_count;
reg [1:0] next_state, current_state;
parameter s0=2'b00, s1=2'b01, s2=2'b10;
always @ (current_state)
case (current_state)
s0: begin
next_state = s1;
end
s1: begin
next_state = s2;
end
s2: begin
next_state = s0;
end
default: begin
next_state = s0;
end
endcase
always@(posedge CLK or negedge RESET_N)
if (~ RESET_N)
begin
current_state <= s0;
end
else
begin
current_state <= next_state;
end
always @ (current_state or a or b or count)
case (current_state)
s0: begin
next_count = (count + 1'd1);
next_c = a + b;
end
s1: begin
next_count = (count + 1'd1);
next_c = a - b;
end
s2: begin
next_count = (count - 1'd1);
next_c = a * b;
end
default: begin
next_count = (count - 1'd1);
next_c = a * b;
end
endcase
always@(posedge CLK or negedge RESET_N)
if (~ RESET_N)
begin
count <= 2'd0;
c <= 6'd0;
end
else
begin
count <= next_count;
c <= next_c;
end
endmodule