module frtl3 (CLK, RESET_N, a, b, c, count);
input CLK;
input RESET_N;
input [5:0] a;
input [5:0] b;
output [5:0] c;
output [1:0] count; // Number of bits is 2 with the msb on the left: count[1].
reg [5:0] c; // Signals written to in an always block are declared as type reg.
reg [1:0] next_state;
reg [1:0] current_state; // Will synthesize to ffs only if the always
reg [1:0] count; // block is sensitive to an edge, i.e., posedge CLK.
parameter s0=2'd0,
s1=2'd1,
s2=2'd2;
always @ (posedge CLK or negedge RESET_N)
if (~ RESET_N)
current_state <= s0;
else
current_state <= next_state;
always @ (current_state)
case (current_state)
s0: next_state = s1;
s1: next_state = s2;
s2: next_state = s0;
default: next_state = s0;
endcase
always @ (posedge CLK or negedge RESET_N) // Clocked process (always block).
if (~ RESET_N) // Active low asynchronous reset.
begin // ~ is the bitwise negation operator.
count <= 2'd0; // # bits = 2; value in decimal is 0.
c <= 6'd0;
end
else
begin
case (current_state)
s0: begin
c <= a + b; // Unsigned modulo addition.
count <= count + 1'd1; // Six-bit rollover counter.
end
s1: begin
c <= a - b; // Outputs count, c are registered.
count <= count + 1'd1;
end
s2: begin
c <= a * b; // Outputs count, c are registered.
count <= count - 1'd1;
end
default: begin // Default state for full case statement.
c <= a * b; // Unsigned modulo multiplication.
count <= count - 1'd1;
end
endcase
end
endmodule