# frtl3.script : dc_shell-t script for frtl3 module. # two procedures: # 1. set_variables procedure: sets some variables. # 2. synthesize procedure: synthesizes frtl3 module. # one verilog source code file used: frtl3.vl proc set_variables {} { # Declare some global variables. global search_path global link_library global target_library global synthetic_library global symbol_library global compile_new_optimization global synlib_prefer_ultra_license global hdlin_report_inferred_modules global fsm_auto_inferring global hdlin_report_fsm global hdlin_infer_enumerated_types # Set some variables. set search_path {.} # should also include libraries/syn path # class.db is a standard cell library in Synopsys database format that # the design will be mapped to in the compile command of the script. set target_library class.db set link_library class.db set symbol_library class.sdb # Set the DC Ultra optimization mode and checkout the DC Ultra license. set_ultra_optimization true # Set which optimization algorithms Design Compiler uses. When true, # the new optimization algorithms in Design Compiler are turned on. # The new optimization algorithms leverage a gain-based delay # model that is automatically derived using library analysis. set compile_new_optimization true set hdlin_report_inferred_modules verbose # Check out a DesignWare Foundation license. set synlib_prefer_ultra_license true # DesignWare Foundation is set as the synthetic library. set synthetic_library dw_foundation.sldb set link_library [ concat $link_library $synthetic_library ] set fsm_auto_inferring true set hdlin_report_fsm true set hdlin_infer_enumerated_types true } proc synthesize {} { # Generate a listing of licenses in use. redirect frtl3.license.rpt { list_license } # The file, frtl3.vl, is checked for errors using the analyze command. # If there's no errors, the verilog is translated to an intermediate format. # The messages generated by the analyze command are redirected to a file, # frtl3.analyze.rpt. echo "analyze command with frtl3.vl started." redirect frtl3.analyze.rpt { set frtl3_analyze_variable [ analyze -f verilog frtl3.vl ] } if {$frtl3_analyze_variable == 1} then { echo "analyze command with frtl3.vl successfully executed." } else { echo "The analyze command with frtl3.vl generated at least one error." set strings [exec grep Error frtl3.analyze.rpt] echo "Error message(s) from analyze frtl3.vl command:" puts $strings echo "Returning from synthesize procedure due to analyze frtl3.vl error(s)." return } echo "elaborate command with the frtl3 module started." redirect frtl3.elaborate.rpt { set frtl3_elaborate_variable [ elaborate frtl3 ] } if {$frtl3_elaborate_variable == 1} then { echo "elaborate command with frtl3 successfully executed." } else { echo "The elaborate command with frtl3 module generated at least one error." set strings [exec grep Error frtl3.elaborate.rpt] echo "Error message(s) from elaborate command with frtl3 module:" puts $strings echo "Returning from synthesize procedure due to elaborate frtl3 error(s)." return } current_design frtl3 set_local_link_library class.db # Obtain a report to see if there are any combinational loops. # If there is a combinational loop the report will state # that a timing loop is detected. # If there is no combinational loop the report will state # that no loops were detected. redirect frtl3.loops.rpt { report_timing -loops } # Check for unwanted latches. The file, frtl3.latch.rpt, should be an # empty file, signifying no latches. redirect frtl3.latch.rpt { all_registers -level_sensitive } create_multibit -name state_reg {current_state*} create_clock CLK -period 6 # Minimize area for a given timing constraint. set_max_area 0.0 # The design is mapped and optimized to the class # standard cell library using the compile command. # The compile log messages are redirected to the file, frtl3.compile.rpt. # Other possible choices of map_effort besides high are medium and low. echo "compile command with the frtl3 module started." redirect frtl3.compile1.rpt { set frtl3_compile_variable [ compile -map_effort high ] } if {$frtl3_compile_variable == 1} then { echo "compile command with frtl3 successfully executed." } else { echo "The compile command with frtl3 module generated at least one error." set strings [exec grep Error frtl3.compile1.rpt] echo "Error message(s) from compile command with frtl3 module:" puts $strings echo "Returning from synthesize procedure due to compile frtl3 error(s)." return } # Check design for warnings and write output to file frtl3_warnings. # An empty file signifies no warnings. redirect frtl3.warnings.rpt { check_design } # Obtain a report summarizing information on how well # the design meets constraints that were specified. redirect frtl3.constraints.rpt { report_constraints } # Obtain a report displaying some information on the current design. redirect frtl3.design.rpt { report_design } # Obtain a report displaying attributes of the current design. redirect frtl3.attributes.rpt { report_attributes } # Write a report listing the number of each type of cell used in the design. redirect frtl3.reference.rpt { report_reference } # Write a report listing the number and type of designware components # implemented in the design for the arithmetic operators, +, -, *, <, >, etc. # In addition this report would include any resource-sharing information. # The report would also include other designware components implemented such # as muxes. redirect frtl3.resources.rpt { report_resources -hierarchy } ungroup -all # Optimize design after previous ungroup command. redirect frtl3.compile2.rpt { compile -incremental_map -map_effort high } # Obtain an area report in units of gates. # Specified as total cell area in report. # Obtain a state machine report. redirect frtl3.fsm.rpt { report_fsm } redirect frtl3.area.rpt { report_area } # The timing report is written to file. # Reports the longest true path delay in the design in nanoseconds. # In the report, if the slack is negative, the design's timing as # specified in the set_max_delay command for a combinational design # or in a create_clock command for a synchronous design is not reached. # The clock period is the sum of the arrival time listed in the Path column # and the absolute value of the library setup time listed in the Incr column. redirect frtl3.timing.rpt { report_timing -true } # Write the design to the file frtl3.db in Synopsys internal database format. # The -hierarchy option is only needed when modules are instantiated. # To read the design back into dc_shell-t, the command is, read_db frtl3.db. write -hierarchy -output frtl3.db echo "script completed." } set_variables synthesize