module frtl1 (CLK, RESET_N, a, b, c, count);
input CLK;
input RESET_N;
input [5:0] a;
input [5:0] b;
output [5:0] c;
output [1:0] count; // Number of bits is 2 with the msb on the left: count[1].
reg [5:0] c; // Signals written to in an always block are declared as type reg.
reg [1:0] state; // Will synthesize to ffs only if the always
reg [1:0] count; // block is sensitive to an edge, i.e., posedge CLK.
parameter
s0=2'd0,
s1=2'd1,
s2=2'd2;
always @ (negedge RESET_N or posedge CLK)
if (~ RESET_N)
begin
state <= s0;
c <= 6'd0;
count <= 2'd0;
end
else
begin
case (state)
s0: begin
c <= a + b; // Unsigned modulo addition.
count <= count + 1'd1; // Two-bit rollover counter.
state <= s1;
end
s1: begin
c <= a - b;
count <= count + 1'd1;
state <= s2;
end
s2: begin
c <= a * b;
count <= count - 1'd1;
state <= s0;
end
default: begin
c <= a * b;
count <= count - 1'd1;
state <= s0;
end
endcase
end
endmodule